// Copyright (C) 1953-2022 NUDT
// Verilog module name - control_packet_dispatch
// Version: V4.1.0.20221206
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module control_packet_dispatch
(
    i_clk,
    i_rst_n,
    
    iv_data,
	i_data_wr,

	ov_data_0,
	o_data_wr_0,
    
	ov_data_1,
	o_data_wr_1      
);

// I/O
// clk & rst
input                   i_clk  ;
input                   i_rst_n; 
// pkt input
input	   [8:0]	    iv_data  ;
input	         	    i_data_wr;
// pkt output to NMA
output reg [8:0]	    ov_data_0    ;
output reg	            o_data_wr_0  ;
// pkt output to osp
output reg [8:0]	    ov_data_1    ;
output reg	            o_data_wr_1  ;
//***************************************************
//      add valid of data and delay 8 cycles
//***************************************************
reg        [134:0]      rv_data;
always @(posedge i_clk or negedge i_rst_n) begin
    if(!i_rst_n) begin
        rv_data         <= 135'b0;
    end
    else begin
        if(i_data_wr)begin
            rv_data     <= {rv_data[125:0],iv_data};
        end
        else begin
            rv_data     <= {rv_data[125:0],9'b0};
        end        
    end
end
//***************************************************
//       receive pit record in ctrl interface
//***************************************************
reg       [1:0]               rv_osp_state;
localparam      IDLE_S              = 2'd0,
                TRANS_DATA0_S       = 2'd1,
                TRANS_DATA1_S       = 2'd2;
always @(posedge i_clk or negedge i_rst_n) begin
    if(!i_rst_n)begin
        ov_data_0      <= 9'b0;
        o_data_wr_0    <= 1'b0;

        ov_data_1      <= 9'b0;
        o_data_wr_1    <= 1'b0;

        rv_osp_state   <= IDLE_S;        
    end
    else begin
        case(rv_osp_state)
            IDLE_S:begin
			    if(rv_data[134])begin//transmit first cycle.
					if(({rv_data[25:18],rv_data[16:9]} == 16'hff01) && (rv_data[7:0] == 8'h06))begin//opensync.
						ov_data_0      <= 9'b0;
						o_data_wr_0    <= 1'b0;

						ov_data_1      <= rv_data[134:126];
						o_data_wr_1    <= 1'b1;

						rv_osp_state   <= TRANS_DATA1_S;  
					end
					else begin 
						ov_data_0         <= rv_data[134:126];
						o_data_wr_0       <= 1'b1;
											
						ov_data_1         <= 9'b0;
						o_data_wr_1       <= 1'b0;
											
						rv_osp_state      <= TRANS_DATA0_S;  
					end                    
                end
                else begin
                    ov_data_0         <= 9'b0;
                    o_data_wr_0       <= 1'b0;
                                        
                    ov_data_1         <= 9'b0;
                    o_data_wr_1       <= 1'b0;
                                        
                    rv_osp_state      <= IDLE_S;                      
                end
            end
            TRANS_DATA0_S:begin
                ov_data_0        <= rv_data[134:126];
                o_data_wr_0      <= 1'b1;              
                if(rv_data[134])begin//last cycle. 
                    rv_osp_state   <= IDLE_S;
                end
                else begin
                    rv_osp_state   <= TRANS_DATA0_S;
                end
            end
            TRANS_DATA1_S:begin
                ov_data_1        <= rv_data[134:126];
                o_data_wr_1      <= 1'b1;              
                if(rv_data[134])begin//last cycle. 
                    rv_osp_state   <= IDLE_S;
                end
                else begin
                    rv_osp_state   <= TRANS_DATA1_S;
                end
            end                       
            default:begin
                ov_data_0      <= 9'b0;
                o_data_wr_0    <= 1'b0;

                ov_data_1      <= 9'b0;
                o_data_wr_1    <= 1'b0;            
            
                rv_osp_state <= IDLE_S;  
            end
        endcase
    end
end
endmodule